Hardening Options

Hardening Your Caravel User Project: Macro, Flat, and Mixed Integration Strategies

This article details the three primary methods for hardening a Caravel user project, focusing on their implementation using the OpenLane flow and the Caravel User Project Example. Understanding these approaches will help you choose the most suitable strategy for your design's complexity, timing requirements, and area utilization.

Introduction to Caravel Hardening

Hardening a Caravel user project involves integrating your custom digital logic (the "user project") into the Caravel SoC platform. This process translates your RTL design into a physical layout (GDSII) that can be fabricated. OpenLane, an automated RTL-to-GDSII flow, is the primary tool used for this purpose. The Caravel User Project Example provides a well-structured starting point for your designs.

Hardening Option 1: Macro hardening and Top-Level Integration

In this approach, your entire user project is hardened as a single, large "hard macro" which is then instantiated and integrated at the Caravel top level. This is ideal for complex designs that benefit from a dedicated, optimized flow for the macro itself, potentially leading to better performance and area for that specific block. The Caravel User Project Wrapper (user_project_wrapper) will essentially be a simple top-level that instantiates your hardened macro.

When to use:

• Your user project is a self-contained, complex block (e.g., a custom CPU, a large DSP block).

• You want to optimize the macro independently.

Macro Hardening:

• Navigate to your user project directory (e.g., caravel_user_project/openlane/user_proj_example).

• Modify config.json for your specific user project.

• Set DESIGN_IS_CORE to 0 for the user project's hardening run. This treats your design as a standalone chip.

• Define all your Verilog files, SDC, and power/ground connections relevant to your user project.

• Run OpenLane: make <design_name>.

• Upon successful completion, you will get the GDSII, LEF, and Verilog netlist for your hardened macro.

Examples for macro hardening:

Caravel User Project

Caravel User SRAM

Top-Level Integration (user_project_wrapper):

• Navigate to the caravel_user_project/openlane/user_project_wrapper directory.

• Modify the user_project_wrapper/config.json.

• Include the generated LEF file of your hardened user project macro in EXTRA_LEF_DIRS or similar.

• Ensure the user_project_wrapper.v instantiates your hardened macro. You will need to replace the placeholder user_proj_example module with your actual macro's instantiation, ensuring port names match your macro's Verilog netlist.

Configuration variables in user_project_wrapper/config.json for top-level integration:

"QUIT_ON_SYNTH_CHECKS": 0,
"FP_PDN_CHECK_NODES": 0,
"SYNTH_ELABORATE_ONLY": 1,
"PL_RANDOM_GLB_PLACEMENT": 1,
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
"GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0,
"GLB_RESIZER_TIMING_OPTIMIZATIONS": 0,
"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
"FP_PDN_ENABLE_RAILS": 0,
"GRT_REPAIR_ANTENNAS": 0,
"RUN_FILL_INSERTION": 0,
"RUN_TAP_DECAP_INSERTION": 0,
"RUN_CTS": 0,
"RUN_CVC": 0,

In this method, your entire user project design, including any sub-modules, is hardened as a single, flat design directly within the user_project_wrapper. There are no separate hard macros. OpenLane processes all your RTL files together to create a single GDSII for the user_project_wrapper. This is the simplest approach and often suitable for smaller to medium-sized designs.

When to use: 

• You want to optimize your design for performance and clock speed.

• You don't require specific optimization for isolated sub-blocks.

• You are fine with OpenLane making global placement and routing decisions across your entire design.

Single OpenLane Run:

• Navigate to the caravel_user_project/openlane/user_project_wrapper directory.

• Modify config.json in this directory.

• Set DESIGN_IS_CORE to 1.

• Include all your user project's Verilog files, along with the user_project_wrapper.v, in VERILOG_FILES. OpenLane will treat them as one design.

• Ensure your user_project_wrapper.v directly instantiates your design's modules or contains your design's logic.

Configuration variables changes in user_project_wrapper/config.json for top-level integration:

"QUIT_ON_SYNTH_CHECKS": 1,
"FP_PDN_CHECK_NODES": 1,
"SYNTH_ELABORATE_ONLY": 0,
"PL_RANDOM_GLB_PLACEMENT": 0,
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 1,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 1,
"GLB_RESIZER_DESIGN_OPTIMIZATIONS": 1,
"GLB_RESIZER_TIMING_OPTIMIZATIONS": 1,
"PL_RESIZER_BUFFER_INPUT_PORTS": 1,
"FP_PDN_ENABLE_RAILS": 1,
"GRT_REPAIR_ANTENNAS": 1,
"RUN_FILL_INSERTION": 1,
"RUN_TAP_DECAP_INSERTION": 1,
"RUN_CTS": 1,
"RUN_CVC": 1,

This approach combines the best of both worlds: you can harden specific, critical blocks as hard macros for independent optimization, while other less critical logic or glue logic remains flat at the user_project_wrapperlevel. This offers flexibility and can be beneficial for designs with distinct functional blocks.

When to use:

• Your user project contains both large, reusable, or performance-critical blocks that benefit from dedicated hardening and smaller, optimizations on the top level for accurate timing results.

• You want fine-grained control over the hardening of specific intellectual property (IP) blocks.

• You need to balance macro optimization with overall integration flexibility.

Macro Hardening (for specific blocks):

1. Follow the steps for "Macro and Top-Level Integration" (Option 1) for each of your hard macros. Each macro will have its own OpenLane run and config.json file.

2. Generate GDSII, LEF, and Verilog netlists for each macro.

Top-Level Integration (user_project_wrapper):

• Navigate to caravel_user_project/openlane/user_project_wrapper.
• Modify user_project_wrapper/config.tcl.
• Set DESIGN_IS_CORE to 1.
• Include the LEF files of all your hardened macros in EXTRA_LEF_DIRS.
• Include the Verilog netlists of your hardened macros in VERILOG_FILES_BLACKBOX for LVS verification.
• Include the Verilog files for any new logic that will be synthesized directly within the user_project_wrapper (i.e., not part of a hardened macro).
• The user_project_wrapper.v will instantiate your hardened macros and also contain the RTL for the "flat" logic.

Configuration variables changes in user_project_wrapper/config.json for top-level integration:

"QUIT_ON_SYNTH_CHECKS": 1,
"FP_PDN_CHECK_NODES": 1,
"SYNTH_ELABORATE_ONLY": 0,
"PL_RANDOM_GLB_PLACEMENT": 0,
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 1,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 1,
"GLB_RESIZER_DESIGN_OPTIMIZATIONS": 1,
"GLB_RESIZER_TIMING_OPTIMIZATIONS": 1,
"PL_RESIZER_BUFFER_INPUT_PORTS": 1,
"FP_PDN_ENABLE_RAILS": 1,
"GRT_REPAIR_ANTENNAS": 1,
"RUN_FILL_INSERTION": 1,
"RUN_TAP_DECAP_INSERTION": 1,
"RUN_CTS": 1,
"RUN_CVC": 1,

Important Considerations for All Approaches:

• IO Planning: Carefully define the input/output ports of your user project and how they connect to the Caravel IOs. The user_project_wrapper is responsible for this interface.

• Power and Ground: Ensure your power and ground connections are correctly defined in your config.json files and handled by OpenLane.

• Timing Constraints (SDC): Accurate SDC files are crucial for successful hardening. Define clock periods, input/output delays, and any multi-cycle paths or false paths.

• Caravel User Project Example: Always start with the provided Caravel User Project Example and adapt it to your needs. This example already has the basic structure for the user_project_wrapper.