ChipCreate: Frequently Asked Questions

ChipCreate is a comprehensive platform designed to democratize silicon chip design and manufacturing. Building on the success of the chipIgnite program's community of over 10,000 members and 600+ fabricated chip designs, ChipCreate provides an affordable path to custom ASIC development through multi-project wafer (MPW) shuttles, standardized reference SoC designs, and a collaborative ecosystem.

The platform is designed to empower innovators, researchers, startups, and educational institutions to bring their silicon designs to life without prohibitive costs or complex processes.

ChipCreate is the next evolution of the chipIgnite program, with several key differences:

• Pricing: ChipCreate projects are priced at $14,950 compared to $9,750
• Manufacturing Schedule: Limited initial schedule with 2 shuttles in 2025 and 3 in 2026, compared to quarterly shuttles with chipIgnite
• Customer Flexibility: ChipCreate offers refund or rollover options if shuttle minimums are not met
• Project Submission: ChipCreate uses GitHub repositories for project design submissions.
• Production Support: Initially focused on prototype volumes with plans to expand to production based on demand
• ReRam: ChipCreate does not initially support ReRam. Future support consideration will depend on customer demand.

ChipCreate serves several key user groups:

• Educational Institutions: Universities and colleges seeking real-world chip fabrication experience for students
• Hardware Startups: Early-stage companies needing an affordable path to prototyping
• Original Equipment Manufacturers (OEMs): Established companies creating intelligent products without deep chip design expertise
• Independent Hardware Developers: Individuals looking to turn open-source designs into physical chips

ChipCreate offers multiple System-on-Chip (SoC) designs:

• Caravel: Standard SoC design with 38 programmable GPIOs and ~10 mm² user area
• Caravan: Bare pad prototyping design with 27 programmable GPIOs, 11 bare pads, and ~10 mm² user area
• OpenFrame: Advanced directly configured IO design with 44 configurable GPIOs and ~15 mm² user area
• Caravel Mini: Compact prototyping design with 36 programmable GPIOs and ~2 mm² user area
• Frigate: Next-generation SoC platform with high-performance pipelined RISC-V core (Hazard3) -- COMING SOON

The designs include RISC-V processors with varying capabilities:

• Basic RISC-V processors in the Caravel, Caravan, and Caravel Mini designs
• Enhanced Hazard3 RISC-V processor in the Frigate series designs

All processors provide appropriate communication interfaces for controlling your custom design.

Depending on the design you choose, you'll have access to:

• 36-44 programmable I/Os supporting both digital and analog interfaces
• Standard communication interfaces (UART, SPI, I2C, etc.)
• Options for specialized I/O configurations in the OpenFrame design

ChipCreate supports both open-source and commercial EDA tool flows:

• Open Source: OpenLane for RTL-to-GDSII digital design flow
• Proprietary: Support for industry-standard commercial tools

The platform includes capabilities such as:

• SoC Editor
• RTL/GL/SDF Simulator
• Synthesis
• Schematic Capture
• SPICE Simulation
• Mixed-Mode Simulation
• Parasitic Extraction
• Physical Verification

ChipCreate supports the SKY130 open-source PDK based on the 130nm Skywater Technology foundry process. Additional foundries and nodes to be considered based on customer demand.

For the base price of $14,950, each project includes:

• Fabrication of your custom chip design
• 100 QFN packaged parts (standard) or bare die option
• A complete EDA design flow
• Automated physical implementation for digital designs
• Pre-designed packaging and evaluation board
• 10 of the 100 QFN parts are assembled on M.2 daughter cards.
• One (1) Caravel evaluation board.
• Test framework and firmware to support post-silicon testing for your project.

The typical timeline from submission to receiving your fabricated chips is approximately 5 months. This includes:

• Design verification and aggregation
• Wafer fabrication
• Packaging and assembly
• Basic testing
• Delivery logistics

If a shuttle does not meet the minimum customer commitment threshold required for launch, you will be offered:

• A full refund of your project fee, or
• The option to roll over your project to the next scheduled shuttle

This flexible approach ensures that customers are not penalized for changes in shuttle scheduling.

Currently, ChipCreate is focused on prototype volumes (100 units per design). We are planning to expand into production volumes based on market demand and customer requirements in the future.

Standard projects include QFN packaging. Bare die options are also available for specialized integration needs.

ChipCreate design submissions only require GDSII files for the user project area to be submitted for fabrication. ChipFoundry will integrated your user area design with a golden copy of your selected SoC or OpenFrame for fabriczation.

The open-source EDA design flow supports standard industry design formats including:

• Verilog/SystemVerilog for RTL design
• SPICE for analog simulation
• Standard cell libraries
• GDSII for physical layout
• Various verification formats

While not included in the base package, design review services are available as an optional add-on. This service can help identify potential issues before fabrication.

Yes, ChipCreate maintains and continues to expand an IP marketplace with:

• Digital IPs: Memory modules, peripheral controllers, timers, interfaces (UART, I2C, SPI, etc.)
• Analog IPs: Amplifiers, comparators, sensors, references, power management
• Mixed-Signal IPs: ADCs, DACs, PLLs, oscillators

ChipCreate provides the mpw_precheck tool that can be run locally and through the ChipFoundry platform. The tool covers a series of checks including physical verification checks. The platform tools also offer simulation capabilities for design validation.

ChipCreate provides comprehensive documentation and tutorials:

• Video tutorials accessible through the platform website
• GitHub repositories with user project designs and tutorials
• Timer design and other beginner-friendly example projects
• Regular webinars and training sessions
• Design examples and case studies from successful projects

Yes, ChipCreate supports an active community through several community sites:

• ChipFoundry server on Discord
• fossi-chat.org

We also support design sharing and collaboration through GitHub

ChipCreate offers tiered support services:

• Community forums and knowledge base (free)
• Basic technical support (included with all projects)
• Premium support packages (additional cost)
• Design review services (additional cost)

The standard pricing is $14,950 per project for standard shuttle participation. This includes 100 QFN packaged parts (or optionally all bare die).

There is an option for an additional 50 bare die for $3000

ChipCreate offers:

• Academic discounts for qualifying educational institutions
• Volume discounts for organizations submitting multiple designs
• Special programs for qualified non-profit research

ChipCreate offers flexible payment options:

• Full payment at reservation
• Deposit and milestone payments
• Refund capability if shuttle minimums are not met

The initial shuttle schedule includes:

• CC2509: Submission deadline September 16, 2025; Delivery February 2026
• CC2511: Submission deadline November 11, 2025; Delivery April 2026
• 2026 Expansion: Three planned shuttles throughout 2026, with specific dates to be determined based on customer demand

You can reserve your spot on an upcoming shuttle by submitting a request to us through this form.

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ChipCreate includes several IP protection mechanisms:

• Restricted and monitored staff access to customer design files
• Support for NDA-protected designs
• Clear IP ownership terms

No. Unlike some earlier programs, ChipCreate is a private shuttle with no open-source requirement for your designs.

You retain full commercial rights to your designs and the resulting chips. There are no royalty or licensing fees for commercial deployment.