chipIgnite IP Catalog
Analog, mixed-signal and system-infrastructure cores — the class of IP that is normally the hardest part of a custom mixed-signal design to source, and the most expensive to build from scratch. Licensed as add-ons to a chipIgnite engagement and enabled in your design environment for the licensed project.
Each block was designed into commercial mixed-signal microcontroller products and built in volume on this process node. None of it was authored for this catalog or lifted from a test chip.
Every macro carries production characterization data across process corners, so timing and electrical behavior are measured quantities — not simulation results.
These blocks have spent years in shipping products, where marginal behavior and integration problems surface in ways pre-silicon verification does not reach.
The designs are fixed production assets. No roadmap churn beneath you, and no risk of being the first customer to exercise a corner of the design.
chipIgnite designs draw on IP from three sources. They differ in what you receive and what you may do with it — and they mix freely within one design. All of it is listed in the ChipFoundry marketplace.
| Source | What it is | What you receive | Fee basis |
|---|---|---|---|
| Commercial IPThis catalog | Commercially developed analog, mixed-signal and infrastructure macros with a volume production history. | Black-box views only | Per-project fee, category tiers |
| Open-source IP | Digital and analog blocks published openly — peripherals, small memories, oscillators, converters, comparators and regulators. | Source you can read, modify and redistribute | FreePermissive open-source license |
| Third-party IP | Blocks offered through the marketplace by other vendors. | Varies by vendor | Per vendor terms |
The three sources overlap by function. Open-source oscillators, converters, comparators and regulators are available alongside the blocks listed here — Commercial IP does not replace the open-source catalog. What separates them is provenance and delivery, not what the block does.
On identifiers. All ChipFoundry IP shares the CF_ prefix regardless of how it is licensed. The prefix identifies the publisher, not the license terms or the delivered form — the marketplace listing for each block states which of the three sources above it belongs to.
The fee shown against each block is its individual license fee. See the licensing model below for how individual and group fees interact.
Converters, comparators and input buffers for the measurement path.
| IP block | Description | Individual |
|---|---|---|
| Delta-Sigma Modulator ADCCF_ADC_DSM20 | Delta-sigma modulator ADC, configurable 12-to-20-bit resolution. Oversampling architecture for high-resolution, low-bandwidth measurement.Applications · Precision sensing, weigh scales, thermocouple and bridge front-ends | $30,800 |
| 12-bit SAR ADCCF_ADC_SAR12 | 12-bit successive-approximation ADC optimized for fast general-purpose conversion with low per-sample energy.Applications · Multi-channel scanning, control loops, general data acquisition | $33,900 |
| 12-to-16-bit SAR ADCCF_ADC_SAR16 | Extended-resolution SAR ADC, configurable 12-to-16-bit. Higher dynamic range where the 12-bit converter is insufficient.Applications · Instrumentation, battery and current monitoring, audio-band capture | $37,000 |
| Continuous-Time ComparatorCF_CMP_CT | Continuous-time comparator providing hardware-speed threshold detection independent of the CPU or conversion pipeline.Applications · Fault and over-current trip, zero-cross detect, wake-on-threshold | $18,500 |
| High-Z Input BufferCF_BUF_HIZ | High input-impedance differential input buffer that minimizes loading on the signal source ahead of the converter.Applications · High-impedance sensors, pH and electrochemical probes, piezo inputs | $18,500 |
Amplification, filtering, DAC output, clock synthesis and channel routing.
| IP block | Description | Individual |
|---|---|---|
| 8-bit Voltage/Current DACCF_DAC_VI8 | 8-bit digital-to-analog converter with both voltage and current output modes.Applications · Programmable references, bias generation, actuator drive | $12,400 |
| 100 MHz System PLLCF_PLL_100M | Phase-locked loop generating a 100 MHz system clock from a 12 MHz input reference.Applications · Core clock synthesis, high-speed peripheral and serial timing | $12,400 |
| M0 Subsystem PLLCF_PLL_M0 | Clock-multiplying PLL for the embedded M0 subsystem.Applications · M0 core and bus clock generation | $10,800 |
| Class AB AmplifierCF_AMP_AB | Class AB amplifier suitable for general signal conditioning and as a programmable-gain front-end stage.Applications · Sensor gain stages, buffering, anti-alias driving | $12,400 |
| Switched-Capacitor Filter/GainCF_SCAP_MF | Multi-function switched-capacitor block configurable as a filter, integrator or gain stage.Applications · Analog filtering, charge integration, correlated double sampling | $12,400 |
| 7-bit DAC & LCD BiasCF_DAC_LCD7 | 500 kHz 7-bit DAC with additional LCD bias output taps; usable as a general reference DAC or as a display bias generator.Applications · Segment LCD bias, adjustable reference rails | $12,400 |
| Analog Multiplexer ToolkitCF_AMUX | Analog switch and multiplexer toolkit for configurable signal routing across multiple input channels.Applications · Multi-channel front-ends, self-test and calibration paths | $12,400 |
Bias, supply, timing and fixed code storage.
| IP block | Description | Individual |
|---|---|---|
| Bandgap ReferenceCF_BGR | Voltage and current bandgap reference providing temperature-stable bias to the surrounding analog blocks.Applications · Master reference for ADC, DAC, LDO and oscillator blocks | $7,700 |
| 1.8 V LDO RegulatorCF_LDO_1V8 | Low-dropout regulator generating a 1.8 V core supply from a 5 V input rail.Applications · On-chip core supply, isolated analog rail generation | $7,700 |
| Synchronous ROMCF_ROM_SYNC | Synchronous ROM macro family in 4K, 8K and 32K configurations.Applications · Boot code, lookup tables, fixed coefficient storage | $6,200 |
| Analog Output BufferCF_BUF_OUT | Analog output buffer capable of driving external loads directly from a DAC output.Applications · Off-chip drive, cable and load buffering | $7,700 |
| Voltage MonitorCF_VMON | Voltage monitor providing brown-out detection and power-good signaling.Applications · Supply supervision, reset qualification, safety interlocks | $6,200 |
| 32 kHz RTC OscillatorCF_OSC_RTC32K | 32 kHz real-time-clock oscillator for timestamping and sleep scheduling.Applications · RTC, event logging, low-power wake timing | $7,700 |
| Crystal Oscillator InterfaceCF_XOSC | Crystal oscillator interface supporting an external crystal for precision frequency accuracy.Applications · Communications timing, metrology, precision timebase | $6,200 |
| M0 Oscillator APBCF_OSC_M0_APB | Internal oscillator for the embedded M0 subsystem, with an APB register interface.Applications · M0-based subsystems, self-contained clocking | $6,200 |
Startup, telemetry, on-chip power conversion and system timing.
| IP block | Description | Individual |
|---|---|---|
| POR & Initialization SequencerCF_POR_SEQ | Power-on-reset and initialization sequencer that brings the die up in a defined order.Applications · Reset generation, trim and startup sequencing | $4,700 |
| On-Die Temperature SensorCF_TSENS | On-die temperature sensor with an integrated ADC.Applications · Thermal protection, reference compensation, die telemetry | $4,700 |
| 24 MHz RC OscillatorCF_OSC_RC24M | Internal main RC oscillator, 24 MHz saw-tooth, requiring no external crystal.Applications · Default system clock, crystal-less designs | $6,200 |
| Low-Speed OscillatorCF_OSC_LS | Low-speed oscillator, selectable 100 kHz / 32 kHz / 1 kHz.Applications · Watchdog, sleep timers, RTC backup | $4,700 |
| Boost DC-DC ConverterCF_DCDC_BOOST | On-chip boost DC-DC converter stepping 3.3 V up to 5 V and above.Applications · Solenoid and motor drive, charge pumps, sensor excitation | $4,700 |
| Dual-Port RAMCF_DPRAM | Dual-port memory supporting simultaneous read and write access from two masters.Applications · DMA buffers, inter-processor mailboxes, line buffers | $6,200 |
| 5-Tap Clock Delay LineCF_CLK_DLY5 | Multi-tap clock delay line with five outputs for timing calibration.Applications · Clock deskew, timing trim, sampling-phase adjustment | $6,200 |
Small-footprint reference, memory and clocking utility cells.
| IP block | Description | Individual |
|---|---|---|
| Precision Reference BufferCF_REFBUF | 1 V / 1.2 V precision reference buffer that drives converter reference inputs.Applications · ADC and DAC reference drive, reference distribution | $3,100 |
| Low-Noise Power SystemCF_LNPWR | Low-noise power system providing an isolated analog supply.Applications · Clean rails for ADC, PLL and other noise-sensitive blocks | $1,600 |
| 16×16 Register FileCF_RF_16X16 | 16 × 16 register-file RAM (256 bits) for fast scratch storage.Applications · Scratch pad, small FIFO, mailbox | $3,100 |
| M0 Low-Speed OscillatorCF_OSC_LS_M0 | Low-speed oscillator for the embedded M0 subsystem; watchdog and RTC compatible.Applications · M0 subsystem watchdog and sleep clocking | $3,100 |
| M0 Crystal OscillatorCF_XOSC_M0 | Crystal oscillator for the embedded M0 subsystem.Applications · M0 subsystem precision clocking | $3,100 |
| M0 ROM MacroCF_ROM_M0 | ROM macro for the embedded M0 subsystem with an M0 bus interface.Applications · M0 boot ROM, fixed firmware images | $1,600 |
Compiled single-port synchronous SRAM. One flat project fee covers all four capacities, in any combination, with unlimited instances — evaluated separately from Categories 1 to 5.
| IP block | Description | Individual |
|---|---|---|
| 4 KB Single-Port SRAMCF_SRAM_1024x32 | 4 KB single-port synchronous SRAM macro (1024 words × 32 bits).Applications · Scratch buffers, stacks, small working memory | — |
| 16 KB Single-Port SRAMCF_SRAM_4096x32 | 16 KB single-port synchronous SRAM macro (4096 words × 32 bits).Applications · Protocol stacks, line buffers, data logging | — |
| 32 KB Single-Port SRAMCF_SRAM_8192x32 | 32 KB single-port synchronous SRAM macro (8192 words × 32 bits).Applications · Application working memory, sensor capture buffers | — |
| 64 KB Single-Port SRAMCF_SRAM_16384x32 | 64 KB single-port synchronous SRAM macro (16384 words × 32 bits).Applications · Large working sets, frame and feature buffers | — |
Pricing is driven by the diversity of unique blocks you select within a category. Three cases cover every selection.
You take one block from a category (or one block from each of several categories).
→ The individual license fee for that block.
You take two or more different blocks from the same category.
→ Their individual fees added together, or the category group fee — whichever is lower.
You instantiate the same licensed block many times in one design.
→ Nothing further. Instancing is unlimited.
The group fee is an option, not a requirement. Taking it unlocks every other block in that category at no further cost, which is worth considering even when the individual fees are close — depending on the category, it generally becomes the cheaper option at two or three blocks. Categories are evaluated independently, so a design might pay individual fees in one and the group fee in another. Only Commercial IP counts toward these categories; open-source and third-party blocks are licensed on their own terms.
| Tier | Category | Blocks | Individual license (per block) | Group license (whole category) |
|---|---|---|---|---|
| T1 | Precision Data Conversion & Input | 5 | $18,500 – $37,000 | $42,900 |
| T2 | Signal Conditioning, Conversion & Routing | 7 | $10,800 – $12,400 | $21,500 |
| T3 | References, Regulation, Clocking & ROM | 8 | $6,200 – $7,700 | $14,300 |
| T4 | System Infrastructure | 7 | $4,700 – $6,200 | $8,600 |
| T5 | Compact Support Blocks | 6 | $1,600 – $3,100 | $4,300 |
| T6 | Single-Port SRAM Macros | 4 | Flat project fee | $2,500 |
Pricing notes. All figures are in USD, per-project license fees for a single chipIgnite design. Fees cover the design license only and are additional to chipIgnite shuttle, mask and assembly charges. Volume production terms — including any production NRE and running royalty that apply once a product passes prototype volumes — are quoted separately.
Commercial terms. Licensing and fabrication are governed by the chipIgnite Commercial Terms, which you accept when placing an order or making a reservation. No separate agreement is executed for IP add-ons. Preliminary: block availability, delivered views and license fees may change without notice.
Every block is delivered as a hard macro — already physically implemented, verified and characterized. You integrate against abstract views rather than source, and every title ships the same view set, prepared to a common standard, so integration effort does not vary from block to block.
| View class | Typical delivered views |
|---|---|
| Blackbox view | LEF abstract carrying pin locations, layer blockages and macro boundary, plus a blackbox Verilog module for synthesis, place-and-route and connectivity checking. |
| Timing model | Liberty (.lib) timing and power models characterized across the SkyWater 130nm process, voltage and temperature corners, for static timing analysis. |
| Behavioral model | Verilog or Verilog-AMS behavioral models for full-chip functional simulation, including real-number models where analog behavior must be observed at the top level. |
| Documentation | Integration guide, pin list, electrical specification and operating conditions for the macro. |
Source views are not part of the license grant. Schematics, transistor-level netlists, RTL and full layout are not released. Macro layout is merged during final assembly and is not delivered to the licensee.
Fabrication route. Licensed IP may be used and fabricated only through ChipFoundry, under ChipFoundry’s engagement with SkyWater Technology Foundry, Inc. ChipFoundry merges the licensed IP into the final GDS and verifies it before delivery to the foundry. You do not receive GDS for licensed IP and cannot submit it for manufacture independently or at another foundry.
Blocks are being onboarded into the design environment in stages. Each title passes the same release process before publication, so a released block carries the full view set above rather than whatever happened to survive from its original development.
Locate candidate blocks in the catalog for the functions your design needs.
Add up the individual fees per category and compare against that category’s group fee.
Ask your chipIgnite contact to confirm the status of each candidate, and register interest in any title not yet onboarded. Onboarding is demand-led, and that request is the signal used to schedule the work.
Confirm the block list and resulting fees. Licensed blocks are then enabled in your design environment for that project.
Pre-verified digital logic and memory blocks you can drop straight into your User Project Area with a Wishbone connection to the Caravel harness.
| IP block | Description | Price |
|---|---|---|
| DFFRAM512B, 1KB, 2KB | Register-based memory (D-flip-flop RAM) options providing fast, low-latency temporary storage. | Free |
| 32-bit Timer/PWMCF_TMR32 | 32-bit timer and pulse-width modulation generator for timing control, interrupt generation and driving external devices. | Free |
| UARTCF_UART | Universal asynchronous receiver/transmitter with programmable baud rate and FIFOs for reliable serial communication. | Free |
| I2S ReceiverCF_I2S | Inter-IC Sound receiver block with a FIFO for connecting to and processing digital audio data streams. | Free |
| I2C Master ControllerCF_I2C | I²C master controller with APB/WB interface for serial communication with low-speed peripherals. | Free |
| AES AcceleratorEF_AES | Hardware acceleration for the symmetric block cipher AES (128/256-bit keys). | Free |
| SHA-256 AcceleratorEF_SHA256 | Hardware implementation of the SHA-256 cryptographic hash function. | Free |
| eFPGAEF_eFPGA | Embedded FPGA fabric for reconfigurable custom logic. | Free |
| PSRAM ControllerEF_PSRAM_CTRL_V2 | Controller for Quad I/O SPI PSRAM. | Free |
| GPIO PeripheralCF_GPIO | Peripheral module for managing and interfacing with Caravel’s configurable I/O pads. Necessary for connecting your custom logic to the chip’s pins. | Free |
| Quad SPI Flash ControllerCF_QSPI_XIP_CTRL | QSPI execute-in-place flash controller with a parameterized direct-mapped cache for high-throughput off-chip data storage access. | Free |
| Quad SPI Flash WriterEF_QSPI_FLASH_WRITER | Peripheral for programming Quad SPI flash memory. | Free |
| Clock & Reset ManagerEF_CLK_RST_V2 | Digital clock and reset manager featuring on-chip crystal oscillator control. | Free |
Blocks offered through the marketplace by other vendors, licensed on their own terms.
| IP block | Description | Price |
|---|---|---|
| Non-Volatile MemoryNeuromorphic_X1 | 32×32 1T1R non-volatile ReRAM for low-power neuromorphic and edge-AI applications. | $5,500 |
Tell us which functions your design needs and we will confirm availability, licensing and fees for your project.
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